1. Field of the Invention
The invention relates to a nonvolatile semiconductor memory device having a hierarchical bit line structure wherein bit lines are formed of a main bit line and sub-bit lines.
2. Description of the Related Art
There is an electrically writable read only memory which is erasable as a block of nonvolatile semiconductor memory devices. The nonvolatile semiconductor memory device has a plurality of memory cells each of which is connected to a corresponding bit line of a plurality of bit lines.
There is currently a trend in forming nonvolatile semiconductor memory devices that bit lines are formed of a main bit line and sub-bit lines, a so-called a hierarchical bit line structure. The reason why the nonvolatile semiconductor memory device employs such a hierarchical bit line structure is to speed up the reading of data stored in a memory cell and to minimize any effect upon memory cells other than the memory cell which is being written.
In the nonvolatile semiconductor memory device having a hierarchical bit line structure, for example, 16 sub-bit lines are selectively connected to 1 main bit line via 16 sub-bit line selection transistors. In the case of a memory matrix having 256 memory cells disposed on 1 main bit line, the hierarchical bit line structure becomes as follows. For example, if bit lines are not structured hierarchically, capacitance components of diffusion layers of 256 memory cells are connected to 1 main bit line as loads. On the other hand, if the bit lines are structured hierarchically, even in the main bit line having a large load of the sub-bit lines and the main bit line, capacitance components connected to the main bit line can be reduced to the sum of capacitance components of 16 memory cells and those of sub-bit lines selection transistors.
Even in the case of writing data in a memory cell (hereinafter simply referred to as when writing data), if the bit lines are not structured hierarchically, the nonvolatile semiconductor memory device is influenced or disturbed by the number of 255 multiplied by guaranteed number of writing. On the other hand, if the bit lines are structured hierarchically, the influence of the nonvolatile semiconductor memory device can be reduced to the number of 15 multiplied by guaranteed number of writing.
Meanwhile, a very high voltage in the range of 10 to 15V is applied to a sub-bit line selection transistor in the case of erasing data from the memory cell (hereinafter referred to as when erasing data). Accordingly, there is a problem that when a thin dioxide film, such as a tunnel oxide film, of each memory cell is repeatedly used, it is electrically broken down.
FIG. 9 shows a schematic view showing a conventional semiconductor device.
In this figure, depicted by 100 is a silicon substrate, 200 is diffusion layers forming a source or a drain electrode, 300 is a gate oxide film, 400 is a first gate (floating gate), 500 is a second gate (so-called a control gate or gate electrode). A potential difference between the first gate 400 and silicon substrate 100 is VCC +7V.
To solve the foregoing problems, and to preclude the danger from electronic breakdown, the thickness of a gate oxide film of the sub-bit line selection transistor is made equal to the thickness (about 150 to 200 angstrom) of a high withstand voltage transistor used in a high voltage generation circuit or row decoder or is made to a special thickness greater than that thickness. However, in either case there is a problem that the number of processes, such as a photolithograph-etching process or oxidizing process, increases a boundary part between gate oxide films or a transistor to be formed in a memory matrix have to be made larger. As a result, an area occupied by the layout of the entire memory matrix increases in the foregoing method.